Electrostatic discharges (ESD) are sudden and transient electric flows that usually occur unseen and unheard and yet can inflict massive damage in sensitive electronic circuits if they have sufficient energy.

The sizes of semiconductor devices and their components (microchips, gate oxide thickness) are ever-shrinking to improve their speed and performance. However, their thin dimensions make them sensitive to the released energy of an ESD event. Common failures associated with ESD are current leakage, contact damage, circuit shorts, gate oxide rupture, and burnout. What is more, ESD failures are neither predictable nor easy to diagnose after they occur.

It can be absolutely miserable for a circuit designer when an expensive component is destroyed by a single touch, or the threat to a manufacturer’s reputation when customers line up for their faulty products to be replaced.

Therefore, ESD protection should get critical consideration during circuit design, parts handling, and final consumer usage from circuit builders, manufacturers, distributors, and hobbyists. Let’s give a quick look at what an electrostatic discharge is and its causes.

What causes electrostatic discharge, or ESD?

A charge buildup resulting in an ESD can be due to the triboelectric effect. Here, friction between two different materials in contact causes an electron imbalance when an electron (or more) shifts from one material to the other. When separated, these materials are electrically charged. An ESD occurs when they come back into contact or either material comes in contact with an uncharged conductive object.

The strength of the discharge is a function of a number of factors, such as the material properties, the pressure applied, humidity in the atmosphere, and temperature. It’s normal to experience harmless sparks when touching door knobs and car doors in dry weather. Although, at voltages exceeding 6000 V they start to become painful for many people.

Apart from triboelectricity, electrostatic charging can occur by induction and conduction. Any charged object has a corresponding electrostatic field. If a conductive material enters this field, a redistribution of charges takes place that can lead to an ESD event.

What are the effects of ESDs in internal circuits?

If an ESD event of sufficient current flows in an integrated circuit, IC, it can cause damage. A catastrophic damage means the device stops functioning, e.g., a thin gate oxide breaks down or a metal junction burns out. Other forms of degradation due to ESD may affect a device’s long-term performance. These are termed latent damage because the affected device will appear to be working normally, only to fail sometime in future.

Therefore, it is important to define a circuit’s ESD immunity and predict its reliability given the circuit’s design and layout.

Classification of ESD sensitivity

Integrated circuits have device-level ESD protection built in. Their effectiveness and reliability when exposed to ESD events are tested according to industry standards using the following models:
● Human Body Model, HBM, that emulates ESD events caused by the human handling
● Machine Model, MM, that emulates ESD events caused by automated machines
● Charged Device model, CDM, that emulates ESD events caused by product charging/discharging

ESD sensitivity using the above models is qualified by the highest and lowest ESD test voltages a device passes and fails respectively.

Methods for ESD protection

In an IC, the current from an ESD event tends to seek the path to ground with the lowest impedance. These currents are on the order of 0.1-10 amps, dissipating energy on the order 10 -100 watts in durations as short as 10-6 seconds. The objective of ESD protection methods is to shunt ESD currents along an intended discharge path and dissipate the energy in ESD devices while clamping the voltage at a safe level to protect components in the circuit.

What is Snapback?

Standard ESD protection devices are voltage clamping devices with high resistance up to a breakdown voltage above which their resistance drops dramatically. They turn on at that point and begin to conduct electricity. For such devices, it is important that their breakdown voltage (turn on) is above the normal operating voltage of the circuit, but low enough that the clamping voltage is below the voltage that can damage the protected circuit.

Zooming in on the internal structure of the solid state ESD device, a free electron (hole) becomes mobile in the presence of an electric field and if the field is low, the electron moves about without incident. On the other hand, a strong electric field produced by a high voltage associated with an ESD event energizes a mobile electron to strike bound electrons free. The free electrons propagate the same action which leads to an avalanche of electrons (breakdown).

Voltage clamping devices are ideally switched off during normal operations (allowing a negligible current through) but begin conducting current once their threshold voltage has been reached.

Snapback ESD protection devices behave differently. The typical MOSFET has a parasitic bipolar junction transistor which has a source as its emitter and drain as its collector.

As the avalanche current flows to the base of the parasitic bipolar junction transistor, the base current can trigger the device to allow current flows between the collector and emitter. Once triggered, the strong electric field that caused the avalanche current is no longer necessary to sustain it. Conduction of large currents continues even at lower voltages. This is the snapback effect, for a high voltage (transient ESD event) to trigger current flows in the device that continues to conduct at a low voltage.

At low voltages, the snapback ESD device also has high resistance and turns on at a voltage greater than normal operating conditions of the protected circuit. What is different is that after it begins to conduct (now with a low resistance), the voltage drops well below the turn on voltage and in some situations, drops into the normal operating range of voltages of the protected circuit. That is, the device could remain in the on state, conducting current even after the ESD event is over. This is referred to as latch-up.

An ESD protection device should be selected such that the voltage at which it triggers is not too high that it can damage sensitive components of the circuit to be protected. Similarly, the lower hold voltage should not be lower than the normal operating voltage of the circuit so that the device switches off after the ESD event ends.

The operation of MOSFET transistors at high currents where impact ionization and the device’s behavior becomes bipolar, are not covered by the usual device equations.

Verifying the effectiveness of an ESD device

I-V characterization curves for ESD devices can be used to verify their proper operation in circuits. The curves can be created using a process called transmission line pulse testing (TLP) whereby controlled and carefully timed square waves are run through the device and a set of measurements are taken.

SPICE simulation is inadequate for modelling the snapback operational behavior. A consequence of the negative differential resistance affecting the convergence of the model. Ignoring snapback or analyzing it incorrectly will produce results that will lead to ESD violations and failure during operation.

Important parameter definitions for selecting effective ESD protection devices

Holding voltage: After the voltage exceeds the trigger voltage and the ESD device experiences snapback, the same or a higher amount of current will flow through the device but at a lower voltage. Provided the minimum voltage is maintained, the device remains in the snapback mode. The device will revert to its normal operating mode (off state and only conducting a small leakage current) if the voltage falls below the holding voltage.

Clamping voltage: The ESD device clamps to this voltage during an ESD event. It is the “safe” voltage the protected circuit will experience. Manufacturer datasheets specify the clamping voltage in different ways that could lead to confusion when comparing devices. When in doubt, consider the dynamic resistance of the devices. Generally, the lower the dynamic resistance, the better clamping-voltage performance.

Dynamic resistance: The effective resistance of the ESD device’s path to ground during an ESD event.

Effective ESD protection will satisfy the following conditions:
● leakage current is low,
● the ESD current in the snapback region is high
● has fast response times
● can repeatedly handle high voltages and currents over short durations

Examples of ESD protection devices are silicon TVS diode arrays, multilayer varistors and polymer ESD suppressors. MOVs and TVS are voltage clamps while polymer suppressors exhibit snapback behavior. At low voltages, the polymer has high resistance but produces voltage arcs between the conducting particles at high voltages, decreasing its resistance. Breakdown voltage is a function of the type of polymer, the sizes of the conducting particles and the distance between them. They are characterized by high trigger voltages exceeding 1000 V, making them unsuitable for sensitive and low voltage operating circuits but excellent for high speed data line applications because of their ultra-low capacitance.